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[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [rtl/] [verilog/] - Rev 109

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Rev Log message Author Age Path
109 Rev2 from trunk unneback 4723d 10h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
107 corrected signal type for ba unneback 4879d 14h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
106 added texinfo User guide and updated fsm unneback 4897d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
105 versatile_mem modules naming unneback 4904d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
104 versatile_mem modules naming unneback 4904d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
102 cleaning up unneback 4935d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
101 cleaning up unneback 4935d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
100 unneback 4935d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
98 updates unneback 5038d 13h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
97 updated tb and sdram16 unneback 5039d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
95 new files unneback 5074d 03h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
86 mikaeljf 5145d 16h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5146d 16h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
84 mikaeljf 5150d 15h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
82 mikaeljf 5151d 14h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
81 mikaeljf 5152d 11h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
80 mikaeljf 5152d 12h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5190d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5192d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5200d 07h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5205d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
75 mikaeljf 5205d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5209d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5209d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5209d 10h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5209d 11h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
70 mikaeljf 5212d 17h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
69 mikaeljf 5213d 13h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
68 cleaqnup unneback 5215d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
67 added FSM for wb if unneback 5215d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/

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