OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 24

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5232d 12h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5240d 05h /versatile_mem_ctrl/trunk/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5242d 01h /versatile_mem_ctrl/trunk/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5246d 04h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5248d 05h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5254d 10h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5255d 07h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5258d 06h /versatile_mem_ctrl/trunk/
16 Added fizzim.pl mikaeljf 5258d 06h /versatile_mem_ctrl/trunk/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5259d 06h /versatile_mem_ctrl/trunk/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5349d 09h /versatile_mem_ctrl/trunk/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5349d 12h /versatile_mem_ctrl/trunk/
12 Minor update of whishbone FSMs in TB mikaeljf 5359d 12h /versatile_mem_ctrl/trunk/
11 Initial version with support for DDR mikaeljf 5360d 00h /versatile_mem_ctrl/trunk/
10 unneback 5387d 08h /versatile_mem_ctrl/trunk/
9 testbench unneback 5387d 08h /versatile_mem_ctrl/trunk/
8 unneback 5483d 04h /versatile_mem_ctrl/trunk/
7 unneback 5483d 04h /versatile_mem_ctrl/trunk/
6 unneback 5483d 04h /versatile_mem_ctrl/trunk/
5 pass initial testing unneback 5483d 05h /versatile_mem_ctrl/trunk/
4 unneback 5484d 08h /versatile_mem_ctrl/trunk/
3 unneback 5484d 10h /versatile_mem_ctrl/trunk/
2 initial unneback 5490d 08h /versatile_mem_ctrl/trunk/
1 The project was created and the structure was created root 5490d 09h /versatile_mem_ctrl/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.