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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 46

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Rev Log message Author Age Path
46 cosmetic updates unneback 5290d 05h /versatile_mem_ctrl/trunk/
45 added unneback 5290d 07h /versatile_mem_ctrl/trunk/
44 registered row comparison unneback 5292d 07h /versatile_mem_ctrl/trunk/
43 unneback 5292d 13h /versatile_mem_ctrl/trunk/
42 added pipeline stage for egress FIFO readot unneback 5292d 21h /versatile_mem_ctrl/trunk/
41 Added two alternate data capture functions. mikaeljf 5293d 04h /versatile_mem_ctrl/trunk/
40 updated fifo interfaces with re/rd and we/wr unneback 5293d 11h /versatile_mem_ctrl/trunk/
39 updated FIFO and SDR 16 unneback 5293d 23h /versatile_mem_ctrl/trunk/
38 casex in rw state to save logic unneback 5296d 06h /versatile_mem_ctrl/trunk/
37 unneback 5296d 21h /versatile_mem_ctrl/trunk/
36 unneback 5296d 21h /versatile_mem_ctrl/trunk/
35 work for limited test case unneback 5297d 05h /versatile_mem_ctrl/trunk/
34 added unneback 5297d 05h /versatile_mem_ctrl/trunk/
33 work for limited test case, no cke inhibit for fifo empty unneback 5297d 07h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5300d 11h /versatile_mem_ctrl/trunk/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5302d 04h /versatile_mem_ctrl/trunk/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5302d 04h /versatile_mem_ctrl/trunk/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5306d 04h /versatile_mem_ctrl/trunk/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5306d 06h /versatile_mem_ctrl/trunk/
27 unneback 5309d 22h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5311d 21h /versatile_mem_ctrl/trunk/
25 unneback 5311d 23h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5312d 11h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5320d 03h /versatile_mem_ctrl/trunk/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5321d 23h /versatile_mem_ctrl/trunk/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5326d 02h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5328d 04h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5334d 08h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5335d 05h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5338d 04h /versatile_mem_ctrl/trunk/

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