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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 112

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Rev Log message Author Age Path
112 ddr3 unneback 4686d 13h /versatile_mem_ctrl/trunk/rtl/
111 major update unneback 4686d 15h /versatile_mem_ctrl/trunk/rtl/
110 files deleted unneback 4686d 15h /versatile_mem_ctrl/trunk/rtl/
107 corrected signal type for ba unneback 4842d 20h /versatile_mem_ctrl/trunk/rtl/
106 added texinfo User guide and updated fsm unneback 4860d 07h /versatile_mem_ctrl/trunk/rtl/
105 versatile_mem modules naming unneback 4867d 14h /versatile_mem_ctrl/trunk/rtl/
104 versatile_mem modules naming unneback 4867d 14h /versatile_mem_ctrl/trunk/rtl/
102 cleaning up unneback 4898d 14h /versatile_mem_ctrl/trunk/rtl/
101 cleaning up unneback 4898d 14h /versatile_mem_ctrl/trunk/rtl/
100 unneback 4898d 14h /versatile_mem_ctrl/trunk/rtl/
98 updates unneback 5001d 19h /versatile_mem_ctrl/trunk/rtl/
97 updated tb and sdram16 unneback 5002d 08h /versatile_mem_ctrl/trunk/rtl/
95 new files unneback 5037d 09h /versatile_mem_ctrl/trunk/rtl/
86 mikaeljf 5108d 21h /versatile_mem_ctrl/trunk/rtl/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5109d 21h /versatile_mem_ctrl/trunk/rtl/
84 mikaeljf 5113d 20h /versatile_mem_ctrl/trunk/rtl/
82 mikaeljf 5114d 20h /versatile_mem_ctrl/trunk/rtl/
81 mikaeljf 5115d 16h /versatile_mem_ctrl/trunk/rtl/
80 mikaeljf 5115d 17h /versatile_mem_ctrl/trunk/rtl/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5153d 07h /versatile_mem_ctrl/trunk/rtl/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5155d 14h /versatile_mem_ctrl/trunk/rtl/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5163d 12h /versatile_mem_ctrl/trunk/rtl/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5168d 13h /versatile_mem_ctrl/trunk/rtl/
75 mikaeljf 5168d 15h /versatile_mem_ctrl/trunk/rtl/
74 Minor update of rtl Makefile. mikaeljf 5172d 14h /versatile_mem_ctrl/trunk/rtl/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5172d 15h /versatile_mem_ctrl/trunk/rtl/
72 Restored lost revisions 69 and 70. mikaeljf 5172d 15h /versatile_mem_ctrl/trunk/rtl/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5172d 16h /versatile_mem_ctrl/trunk/rtl/
70 mikaeljf 5175d 22h /versatile_mem_ctrl/trunk/rtl/
69 mikaeljf 5176d 19h /versatile_mem_ctrl/trunk/rtl/

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