URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 28

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Rev	Log message	Author	Age	Path
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5266d 04h	/versatile_mem_ctrl/trunk/rtl/
27		unneback	5269d 19h	/versatile_mem_ctrl/trunk/rtl/
26	compiles OK, not simulated	unneback	5271d 18h	/versatile_mem_ctrl/trunk/rtl/
25		unneback	5271d 21h	/versatile_mem_ctrl/trunk/rtl/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5272d 08h	/versatile_mem_ctrl/trunk/rtl/
23	Removed redundant code.	mikaeljf	5280d 01h	/versatile_mem_ctrl/trunk/rtl/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5281d 21h	/versatile_mem_ctrl/trunk/rtl/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5286d 00h	/versatile_mem_ctrl/trunk/rtl/
20	Minor update of sdc-file.	mikaeljf	5288d 02h	/versatile_mem_ctrl/trunk/rtl/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5294d 06h	/versatile_mem_ctrl/trunk/rtl/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5295d 03h	/versatile_mem_ctrl/trunk/rtl/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5298d 02h	/versatile_mem_ctrl/trunk/rtl/
16	Added fizzim.pl	mikaeljf	5298d 03h	/versatile_mem_ctrl/trunk/rtl/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5299d 03h	/versatile_mem_ctrl/trunk/rtl/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5389d 08h	/versatile_mem_ctrl/trunk/rtl/
11	Initial version with support for DDR	mikaeljf	5399d 20h	/versatile_mem_ctrl/trunk/rtl/
7		unneback	5523d 01h	/versatile_mem_ctrl/trunk/rtl/
6		unneback	5523d 01h	/versatile_mem_ctrl/trunk/rtl/
5	pass initial testing	unneback	5523d 01h	/versatile_mem_ctrl/trunk/rtl/
4		unneback	5524d 04h	/versatile_mem_ctrl/trunk/rtl/
3		unneback	5524d 07h	/versatile_mem_ctrl/trunk/rtl/
2	initial	unneback	5530d 05h	/versatile_mem_ctrl/trunk/rtl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 28

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