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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 48

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Rev Log message Author Age Path
48 dq_oe fix unneback 5256d 16h /versatile_mem_ctrl/trunk/rtl/
47 support for registered outputs on ras, cas and we unneback 5256d 17h /versatile_mem_ctrl/trunk/rtl/
46 cosmetic updates unneback 5256d 18h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5256d 20h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5258d 20h /versatile_mem_ctrl/trunk/rtl/
42 added pipeline stage for egress FIFO readot unneback 5259d 09h /versatile_mem_ctrl/trunk/rtl/
41 Added two alternate data capture functions. mikaeljf 5259d 17h /versatile_mem_ctrl/trunk/rtl/
40 updated fifo interfaces with re/rd and we/wr unneback 5260d 00h /versatile_mem_ctrl/trunk/rtl/
39 updated FIFO and SDR 16 unneback 5260d 11h /versatile_mem_ctrl/trunk/rtl/
38 casex in rw state to save logic unneback 5262d 19h /versatile_mem_ctrl/trunk/rtl/
37 unneback 5263d 09h /versatile_mem_ctrl/trunk/rtl/
36 unneback 5263d 10h /versatile_mem_ctrl/trunk/rtl/
35 work for limited test case unneback 5263d 17h /versatile_mem_ctrl/trunk/rtl/
34 added unneback 5263d 18h /versatile_mem_ctrl/trunk/rtl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5263d 20h /versatile_mem_ctrl/trunk/rtl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5267d 00h /versatile_mem_ctrl/trunk/rtl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 17h /versatile_mem_ctrl/trunk/rtl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 17h /versatile_mem_ctrl/trunk/rtl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5272d 19h /versatile_mem_ctrl/trunk/rtl/
27 unneback 5276d 10h /versatile_mem_ctrl/trunk/rtl/
26 compiles OK, not simulated unneback 5278d 09h /versatile_mem_ctrl/trunk/rtl/
25 unneback 5278d 12h /versatile_mem_ctrl/trunk/rtl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5278d 23h /versatile_mem_ctrl/trunk/rtl/
23 Removed redundant code. mikaeljf 5286d 16h /versatile_mem_ctrl/trunk/rtl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5288d 12h /versatile_mem_ctrl/trunk/rtl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5292d 15h /versatile_mem_ctrl/trunk/rtl/
20 Minor update of sdc-file. mikaeljf 5294d 17h /versatile_mem_ctrl/trunk/rtl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5300d 21h /versatile_mem_ctrl/trunk/rtl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5301d 18h /versatile_mem_ctrl/trunk/rtl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5304d 17h /versatile_mem_ctrl/trunk/rtl/

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