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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 64

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Rev Log message Author Age Path
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5212d 21h /versatile_mem_ctrl/trunk/rtl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5213d 04h /versatile_mem_ctrl/trunk/rtl/
62 Added note to sdr_16_defines.v asking if it's still used julius 5213d 06h /versatile_mem_ctrl/trunk/rtl/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5217d 04h /versatile_mem_ctrl/trunk/rtl/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5217d 04h /versatile_mem_ctrl/trunk/rtl/
59 counter changed to shift register unneback 5217d 06h /versatile_mem_ctrl/trunk/rtl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5218d 07h /versatile_mem_ctrl/trunk/rtl/
57 added support for early termination of burst access unneback 5219d 10h /versatile_mem_ctrl/trunk/rtl/
56 corrected fifo_rd_data in state w4d unneback 5221d 02h /versatile_mem_ctrl/trunk/rtl/
55 Fixed up sdr16 dqm output julius 5221d 21h /versatile_mem_ctrl/trunk/rtl/
54 dqm moved into FSM unneback 5222d 18h /versatile_mem_ctrl/trunk/rtl/
53 unneback 5222d 18h /versatile_mem_ctrl/trunk/rtl/
52 act exit for read updated unneback 5223d 20h /versatile_mem_ctrl/trunk/rtl/
51 act exit for read updated unneback 5223d 20h /versatile_mem_ctrl/trunk/rtl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5223d 22h /versatile_mem_ctrl/trunk/rtl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5224d 00h /versatile_mem_ctrl/trunk/rtl/
48 dq_oe fix unneback 5224d 00h /versatile_mem_ctrl/trunk/rtl/
47 support for registered outputs on ras, cas and we unneback 5224d 00h /versatile_mem_ctrl/trunk/rtl/
46 cosmetic updates unneback 5224d 01h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5224d 04h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5226d 04h /versatile_mem_ctrl/trunk/rtl/
42 added pipeline stage for egress FIFO readot unneback 5226d 17h /versatile_mem_ctrl/trunk/rtl/
41 Added two alternate data capture functions. mikaeljf 5227d 01h /versatile_mem_ctrl/trunk/rtl/
40 updated fifo interfaces with re/rd and we/wr unneback 5227d 08h /versatile_mem_ctrl/trunk/rtl/
39 updated FIFO and SDR 16 unneback 5227d 19h /versatile_mem_ctrl/trunk/rtl/
38 casex in rw state to save logic unneback 5230d 03h /versatile_mem_ctrl/trunk/rtl/
37 unneback 5230d 17h /versatile_mem_ctrl/trunk/rtl/
36 unneback 5230d 18h /versatile_mem_ctrl/trunk/rtl/
35 work for limited test case unneback 5231d 01h /versatile_mem_ctrl/trunk/rtl/
34 added unneback 5231d 01h /versatile_mem_ctrl/trunk/rtl/

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