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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 73

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Rev Log message Author Age Path
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5261d 15h /versatile_mem_ctrl/trunk/rtl/
72 Restored lost revisions 69 and 70. mikaeljf 5261d 15h /versatile_mem_ctrl/trunk/rtl/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5261d 16h /versatile_mem_ctrl/trunk/rtl/
70 mikaeljf 5264d 22h /versatile_mem_ctrl/trunk/rtl/
69 mikaeljf 5265d 19h /versatile_mem_ctrl/trunk/rtl/
68 cleaqnup unneback 5267d 07h /versatile_mem_ctrl/trunk/rtl/
67 added FSM for wb if unneback 5267d 07h /versatile_mem_ctrl/trunk/rtl/
66 unneback 5267d 10h /versatile_mem_ctrl/trunk/rtl/
65 added unneback 5267d 10h /versatile_mem_ctrl/trunk/rtl/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5268d 10h /versatile_mem_ctrl/trunk/rtl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5268d 17h /versatile_mem_ctrl/trunk/rtl/
62 Added note to sdr_16_defines.v asking if it's still used julius 5268d 19h /versatile_mem_ctrl/trunk/rtl/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5272d 17h /versatile_mem_ctrl/trunk/rtl/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5272d 17h /versatile_mem_ctrl/trunk/rtl/
59 counter changed to shift register unneback 5272d 19h /versatile_mem_ctrl/trunk/rtl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5273d 20h /versatile_mem_ctrl/trunk/rtl/
57 added support for early termination of burst access unneback 5274d 23h /versatile_mem_ctrl/trunk/rtl/
56 corrected fifo_rd_data in state w4d unneback 5276d 15h /versatile_mem_ctrl/trunk/rtl/
55 Fixed up sdr16 dqm output julius 5277d 10h /versatile_mem_ctrl/trunk/rtl/
54 dqm moved into FSM unneback 5278d 07h /versatile_mem_ctrl/trunk/rtl/
53 unneback 5278d 08h /versatile_mem_ctrl/trunk/rtl/
52 act exit for read updated unneback 5279d 09h /versatile_mem_ctrl/trunk/rtl/
51 act exit for read updated unneback 5279d 09h /versatile_mem_ctrl/trunk/rtl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5279d 11h /versatile_mem_ctrl/trunk/rtl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5279d 13h /versatile_mem_ctrl/trunk/rtl/
48 dq_oe fix unneback 5279d 13h /versatile_mem_ctrl/trunk/rtl/
47 support for registered outputs on ras, cas and we unneback 5279d 14h /versatile_mem_ctrl/trunk/rtl/
46 cosmetic updates unneback 5279d 14h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5279d 17h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5281d 17h /versatile_mem_ctrl/trunk/rtl/

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