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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 110

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Rev Log message Author Age Path
110 files deleted unneback 4739d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
107 corrected signal type for ba unneback 4895d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
106 added texinfo User guide and updated fsm unneback 4913d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
105 versatile_mem modules naming unneback 4920d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
104 versatile_mem modules naming unneback 4920d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
102 cleaning up unneback 4951d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
101 cleaning up unneback 4951d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
100 unneback 4951d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
98 updates unneback 5054d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
97 updated tb and sdram16 unneback 5055d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
95 new files unneback 5090d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
86 mikaeljf 5161d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5162d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
84 mikaeljf 5166d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
82 mikaeljf 5167d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
81 mikaeljf 5168d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
80 mikaeljf 5168d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5206d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5208d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5216d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5221d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
75 mikaeljf 5221d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5225d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5225d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5225d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5225d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
70 mikaeljf 5228d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
69 mikaeljf 5229d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
68 cleaqnup unneback 5231d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
67 added FSM for wb if unneback 5231d 07h /versatile_mem_ctrl/trunk/rtl/verilog/

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