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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
46 cosmetic updates unneback 5227d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
45 added unneback 5227d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
44 registered row comparison unneback 5229d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
42 added pipeline stage for egress FIFO readot unneback 5229d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
41 Added two alternate data capture functions. mikaeljf 5230d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
40 updated fifo interfaces with re/rd and we/wr unneback 5230d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
39 updated FIFO and SDR 16 unneback 5230d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
38 casex in rw state to save logic unneback 5233d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
37 unneback 5233d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
36 unneback 5233d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
35 work for limited test case unneback 5234d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
34 added unneback 5234d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
33 work for limited test case, no cke inhibit for fifo empty unneback 5234d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5237d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5243d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5246d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5248d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5248d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5249d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5257d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5258d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5263d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
20 Minor update of sdc-file. mikaeljf 5265d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5271d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5272d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5275d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
16 Added fizzim.pl mikaeljf 5275d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5276d 04h /versatile_mem_ctrl/trunk/rtl/verilog/

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