| Rev |
Log message |
Author |
Age |
Path |
| 78 |
Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun |
julius |
5187d 05h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 77 |
SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 |
julius |
5195d 04h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 76 |
Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now |
julius |
5200d 05h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 75 |
|
mikaeljf |
5200d 06h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 74 |
Minor update of rtl Makefile. |
mikaeljf |
5204d 05h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 73 |
Minor updates to fix lost revisions 69 and 70. |
mikaeljf |
5204d 06h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 72 |
Restored lost revisions 69 and 70. |
mikaeljf |
5204d 07h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 71 |
Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes |
julius |
5204d 07h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 70 |
|
mikaeljf |
5207d 14h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 69 |
|
mikaeljf |
5208d 10h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 68 |
cleaqnup |
unneback |
5209d 22h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 67 |
added FSM for wb if |
unneback |
5209d 23h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 66 |
|
unneback |
5210d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 65 |
added |
unneback |
5210d 02h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 64 |
Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file |
julius |
5211d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 63 |
Fixed a couple of sdr_16 bugs to do with tracking of opened banks |
julius |
5211d 08h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 62 |
Added note to sdr_16_defines.v asking if it's still used |
julius |
5211d 10h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 61 |
Fixed blocking/nonblocking assign issue in sdr_16 fsm |
julius |
5215d 09h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 60 |
Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. |
julius |
5215d 09h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 59 |
counter changed to shift register |
unneback |
5215d 10h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 58 |
sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm |
julius |
5216d 11h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 57 |
added support for early termination of burst access |
unneback |
5217d 14h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 56 |
corrected fifo_rd_data in state w4d |
unneback |
5219d 07h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 55 |
Fixed up sdr16 dqm output |
julius |
5220d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 54 |
dqm moved into FSM |
unneback |
5220d 23h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 53 |
|
unneback |
5220d 23h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 52 |
act exit for read updated |
unneback |
5222d 00h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 51 |
act exit for read updated |
unneback |
5222d 00h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 50 |
Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily |
julius |
5222d 03h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
| 49 |
Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project |
julius |
5222d 04h |
/versatile_mem_ctrl/trunk/rtl/verilog/ |
