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[/] [vga_lcd/] [tags/] [rel_1/] - Rev 62

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Rev	Log message	Author	Age	Path
62	New directory structure.	root	5578d 08h	/vga_lcd/tags/rel_1/
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8094d 07h	/tags/rel_1/
41	specs version 1.1	rherveille	8094d 07h	/trunk/
40	no message	rherveille	8094d 07h	/trunk/
39	Changed video timing generator. Changed wishbone master vertical gate count code. Fixed a potential bug in the wishbone slave (cursor color register readout).	rherveille	8094d 09h	/trunk/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8094d 09h	/trunk/
37	Fixed a potential reset bug in the hint & vint generation.	rherveille	8109d 12h	/trunk/
36	Fixed two small bugs that only showed up when the hardware cursors were disabled	rherveille	8117d 14h	/trunk/
35	no message	rherveille	8117d 17h	/trunk/
34	Added hardware cursor support to wishbone master. Added provision to turn-off 3D cursors. Fixed some minor bugs.	rherveille	8141d 03h	/trunk/
33	Added 64x64pixels 4bpp hardware cursor support.	rherveille	8141d 08h	/trunk/
32	Fixed dat_o incomplete sensitivity list.	rherveille	8148d 12h	/trunk/
31	Some minor bug-fixes. Changed vga_ssel into vga_curproc (cursor processor).	rherveille	8157d 08h	/trunk/
30	Fixed some bugs discovered by modified testbench Removed / Changed some strange logic constructions Started work on hardware cursor support (not finished yet) Changed top-level name to vga_enh_top.v	rherveille	8166d 13h	/trunk/
29	Added wb_ack delay section to testbench	rherveille	8166d 13h	/trunk/
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8176d 15h	/trunk/
27	Added 32bpp Fixed some typos Added bandwidth section	rherveille	8176d 15h	/trunk/
26	Added 32bpp tests	rherveille	8176d 15h	/trunk/
25	C-include file. Initial release	rherveille	8243d 09h	/trunk/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8250d 12h	/trunk/
23	Added Copyright/Licence header	rherveille	8251d 07h	/trunk/
22	VGA Core v2.0 Document revision 0.7	rherveille	8271d 04h	/trunk/
21	VGA Core v2.0 Document revision 0.7	rherveille	8271d 04h	/trunk/
20	Switched parameter order.	rherveille	8280d 08h	/trunk/
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8280d 10h	/trunk/
18	Removed files. They are not used anymore.	rherveille	8309d 07h	/trunk/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8309d 07h	/trunk/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8336d 13h	/trunk/
15	Created directory structure (documentation, vhdl, verilog)	rherveille	8372d 03h	/trunk/
14	Added CLUT bank switching. Replaced multiplier with simple counters. Fixed timing bug.	rherveille	8372d 22h	/trunk/

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Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_1/] - Rev 62

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