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Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] - Rev 62

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Rev Log message Author Age Path
62 New directory structure. root 5586d 18h /vga_lcd/trunk/rtl/
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7634d 16h /trunk/rtl/
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7663d 13h /trunk/rtl/
55 Initial release. rherveille 7720d 13h /trunk/rtl/
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7720d 18h /trunk/rtl/
45 Changed timing generator; made it smaller and easier. rherveille 7769d 15h /trunk/rtl/
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7770d 06h /trunk/rtl/
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8102d 18h /trunk/rtl/
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8117d 22h /trunk/rtl/
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8125d 23h /trunk/rtl/
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8149d 12h /trunk/rtl/
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8149d 17h /trunk/rtl/
32 Fixed dat_o incomplete sensitivity list. rherveille 8156d 22h /trunk/rtl/
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8165d 17h /trunk/rtl/
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8174d 22h /trunk/rtl/
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8185d 00h /trunk/rtl/
23 Added Copyright/Licence header rherveille 8259d 16h /trunk/rtl/
20 Switched parameter order. rherveille 8288d 18h /trunk/rtl/
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8288d 19h /trunk/rtl/
18 Removed files. They are not used anymore. rherveille 8317d 16h /trunk/rtl/
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8317d 16h /trunk/rtl/
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8344d 22h /trunk/rtl/

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