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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 36

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Rev Log message Author Age Path
36 Updated documentation fransschreuder 2860d 04h /virtex7_pcie_dma/
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2914d 08h /virtex7_pcie_dma/
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 3020d 03h /virtex7_pcie_dma/
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 3065d 02h /virtex7_pcie_dma/
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 3065d 02h /virtex7_pcie_dma/
31 Added example application documentation. oussamak 3159d 04h /virtex7_pcie_dma/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3159d 05h /virtex7_pcie_dma/
29 Improved application to reflect both up and down transfers fransschreuder 3201d 02h /virtex7_pcie_dma/
28 Added registermap reset fransschreuder 3201d 04h /virtex7_pcie_dma/
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3201d 07h /virtex7_pcie_dma/
26 Added sys_clk constraint fransschreuder 3201d 10h /virtex7_pcie_dma/
25 Added scripts and constraints for KCU105 fransschreuder 3201d 10h /virtex7_pcie_dma/
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3202d 03h /virtex7_pcie_dma/
23 Fixed reset of application registers fransschreuder 3259d 09h /virtex7_pcie_dma/
22 Added dma_soft_reset to trigger register resets fransschreuder 3265d 09h /virtex7_pcie_dma/
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3274d 06h /virtex7_pcie_dma/
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3288d 04h /virtex7_pcie_dma/
19 * driver/README updated oussamak 3294d 06h /virtex7_pcie_dma/
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3294d 08h /virtex7_pcie_dma/
17 Changed name of toplevel, to make tree consistent oussamak 3308d 11h /virtex7_pcie_dma/
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3358d 05h /virtex7_pcie_dma/
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3358d 05h /virtex7_pcie_dma/
14 RENAMED:
-- simulation folder		 aborga 3358d 06h /virtex7_pcie_dma/
13 RENAMED:
-- script		 aborga 3358d 06h /virtex7_pcie_dma/
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3433d 06h /virtex7_pcie_dma/
11 MODIFIED:
-- updated documentation		 aborga 3446d 04h /virtex7_pcie_dma/
10 Changed:
LOC => Package_pin		 fransschreuder 3456d 04h /virtex7_pcie_dma/
9 Added actual version information (Build date and svn revision) in BOARD_ID register fransschreuder 3485d 02h /virtex7_pcie_dma/
8 Changed:
* Added support for circular DMA (wrap around)
* Fixed Read / Write interrupts		 fransschreuder 3485d 09h /virtex7_pcie_dma/
7 Changed:
* Simplified address calculation to relax timing
* Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing
* Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk
* Added support for the High tech Global HTG710 board		 fransschreuder 3525d 05h /virtex7_pcie_dma/

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