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Rev Log message Author Age Path
27 Subversion test, no actual code changes rehayes 5384d 23h /xgate/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5387d 02h /xgate/
25 Fix connected net name rehayes 5387d 02h /xgate/
24 Delete unused inputs rehayes 5387d 03h /xgate/
23 Oct 7, 2009 Update rehayes 5393d 00h /xgate/
22 Updated with figures and some new features rehayes 5393d 00h /xgate/
21 Added timeout, total error count, and XGCHN test rehayes 5393d 00h /xgate/
20 Added event signal for compare error tracking in top level test bench. rehayes 5393d 00h /xgate/
19 Verilog memory image for testing rehayes 5393d 00h /xgate/
18 Complete XGCHN test code rehayes 5393d 00h /xgate/
17 Additions for XGCHID debug commands rehayes 5393d 00h /xgate/
16 Copy of what was in the bench directory rehayes 5393d 01h /xgate/
15 Fix R1 load at boot up, add debug features rehayes 5405d 22h /xgate/
14 Sept 23 2009 Change update rehayes 5407d 01h /xgate/
13 Debug functions test code rehayes 5407d 01h /xgate/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5407d 01h /xgate/
11 Update with Single Step debuging test rehayes 5407d 01h /xgate/
10 Minor Cleanup rehayes 5412d 01h /xgate/
9 Update for new testbench usage rehayes 5412d 23h /xgate/
8 Clean up, Fix default ISR rehayes 5412d 23h /xgate/
7 Fix to take advantage of change to sconv program. rehayes 5418d 22h /xgate/
6 Update to create output file name from input file name by changing extension to .v rehayes 5418d 22h /xgate/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5420d 01h /xgate/
4 Clean up rehayes 5427d 22h /xgate/
3 Clean up rehayes 5427d 22h /xgate/
2 Initial Checkin rehayes 5427d 23h /xgate/
1 The project was created and the structure was created root 5460d 03h /xgate/

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