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Rev Log message Author Age Path
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5279d 17h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5279d 18h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5279d 18h /xgate/
58 WISHBONE Bus update. rehayes 5331d 17h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5331d 20h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5347d 21h /xgate/
55 Minor change to instruction set details. rehayes 5347d 21h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5347d 21h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5347d 21h /xgate/
52 Minor changes to aide waveform debug rehayes 5347d 21h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5363d 17h /xgate/
50 incremental update to match status bit changes rehayes 5363d 18h /xgate/
49 First pass with instruction set details rehayes 5363d 18h /xgate/
48 Update for SBC ana ADC condition code changes rehayes 5363d 18h /xgate/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5363d 18h /xgate/
46 Update to remove stack registers and add new register text. rehayes 5395d 16h /xgate/
45 Update to remove stack registers and add new register text. rehayes 5395d 16h /xgate/
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5397d 15h /xgate/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5397d 15h /xgate/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5397d 15h /xgate/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5398d 17h /xgate/
40 Update for single program counter adder rehayes 5418d 20h /xgate/
39 delete rehayes 5426d 21h /xgate/
38 Nov 9 2009 update notes rehayes 5426d 22h /xgate/
37 RAM model breakout for testbench rehayes 5426d 22h /xgate/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5426d 22h /xgate/
35 Add byte lane select input to all tasks rehayes 5426d 22h /xgate/
34 minor changes related to wishbone master interface rehayes 5426d 22h /xgate/
33 Update with some new pin information rehayes 5426d 22h /xgate/
32 added ram block rehayes 5426d 23h /xgate/

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