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Rev Log message Author Age Path
64 Fixed more bugs related to wait states and debug mode. rehayes 5198d 09h /xgate/
63 Remove historical output ports that are no longer used. rehayes 5208d 09h /xgate/
62 Cleanup implicit wire declarations. rehayes 5208d 09h /xgate/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5215d 08h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5215d 08h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 08h /xgate/
58 WISHBONE Bus update. rehayes 5267d 08h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5267d 11h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5283d 12h /xgate/
55 Minor change to instruction set details. rehayes 5283d 12h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 12h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 12h /xgate/
52 Minor changes to aide waveform debug rehayes 5283d 12h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5299d 08h /xgate/
50 incremental update to match status bit changes rehayes 5299d 08h /xgate/
49 First pass with instruction set details rehayes 5299d 09h /xgate/
48 Update for SBC ana ADC condition code changes rehayes 5299d 09h /xgate/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5299d 09h /xgate/
46 Update to remove stack registers and add new register text. rehayes 5331d 07h /xgate/
45 Update to remove stack registers and add new register text. rehayes 5331d 07h /xgate/
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5333d 06h /xgate/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5333d 06h /xgate/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5333d 06h /xgate/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 08h /xgate/
40 Update for single program counter adder rehayes 5354d 11h /xgate/
39 delete rehayes 5362d 12h /xgate/
38 Nov 9 2009 update notes rehayes 5362d 13h /xgate/
37 RAM model breakout for testbench rehayes 5362d 13h /xgate/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5362d 13h /xgate/
35 Add byte lane select input to all tasks rehayes 5362d 13h /xgate/

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