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[/] [xgate/] - Rev 72

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Rev	Log message	Author	Age	Path
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5166d 09h	/xgate/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5167d 12h	/xgate/
70	Updated with interrupt bypass controll registers.	rehayes	5167d 12h	/xgate/
69	New test to verify irq interrupt priority encoder.	rehayes	5167d 12h	/xgate/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5167d 12h	/xgate/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5167d 12h	/xgate/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5187d 08h	/xgate/
65	Parameterize delays based on number of RAM wait states.	rehayes	5187d 08h	/xgate/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5187d 08h	/xgate/
63	Remove historical output ports that are no longer used.	rehayes	5197d 08h	/xgate/
62	Cleanup implicit wire declarations.	rehayes	5197d 08h	/xgate/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5204d 07h	/xgate/
60	Add ability at insert wait states on RAM access	rehayes	5204d 08h	/xgate/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5204d 08h	/xgate/
58	WISHBONE Bus update.	rehayes	5256d 07h	/xgate/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5256d 10h	/xgate/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5272d 11h	/xgate/
55	Minor change to instruction set details.	rehayes	5272d 11h	/xgate/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5272d 11h	/xgate/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5272d 11h	/xgate/
52	Minor changes to aide waveform debug	rehayes	5272d 11h	/xgate/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5288d 07h	/xgate/
50	incremental update to match status bit changes	rehayes	5288d 08h	/xgate/
49	First pass with instruction set details	rehayes	5288d 08h	/xgate/
48	Update for SBC ana ADC condition code changes	rehayes	5288d 08h	/xgate/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5288d 08h	/xgate/
46	Update to remove stack registers and add new register text.	rehayes	5320d 06h	/xgate/
45	Update to remove stack registers and add new register text.	rehayes	5320d 07h	/xgate/
44	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5322d 05h	/xgate/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5322d 05h	/xgate/

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[/] [xgate/] - Rev 72

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