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Rev Log message Author Age Path
79 Added IRQ bypass registers and Test bench appendix rehayes 5140d 23h /xgate/
78 Added IRQ bypass registers and Test bench appendix rehayes 5140d 23h /xgate/
77 Documentation update rehayes 5140d 23h /xgate/
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5164d 00h /xgate/
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5164d 00h /xgate/
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5169d 01h /xgate/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5169d 01h /xgate/
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5169d 01h /xgate/
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5170d 04h /xgate/
70 Updated with interrupt bypass controll registers. rehayes 5170d 04h /xgate/
69 New test to verify irq interrupt priority encoder. rehayes 5170d 04h /xgate/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5170d 04h /xgate/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5170d 05h /xgate/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5190d 00h /xgate/
65 Parameterize delays based on number of RAM wait states. rehayes 5190d 00h /xgate/
64 Fixed more bugs related to wait states and debug mode. rehayes 5190d 00h /xgate/
63 Remove historical output ports that are no longer used. rehayes 5200d 00h /xgate/
62 Cleanup implicit wire declarations. rehayes 5200d 00h /xgate/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5206d 23h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5207d 00h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5207d 00h /xgate/
58 WISHBONE Bus update. rehayes 5258d 23h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5259d 02h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5275d 03h /xgate/
55 Minor change to instruction set details. rehayes 5275d 03h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5275d 03h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5275d 03h /xgate/
52 Minor changes to aide waveform debug rehayes 5275d 03h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5291d 00h /xgate/
50 incremental update to match status bit changes rehayes 5291d 00h /xgate/

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