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[/] [xgate/] [trunk/] - Rev 92

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Rev Log message Author Age Path
92 Add sync reset to bypass register. rehayes 4610d 12h /xgate/trunk/
91 Update to use one ISR to handle all 127 interrupts. rehayes 4610d 12h /xgate/trunk/
90 Cosmetic omment changes. rehayes 4610d 12h /xgate/trunk/
89 Code cleanup. rehayes 4624d 11h /xgate/trunk/
88 Updated with complete code rehayes 4697d 20h /xgate/trunk/
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4824d 10h /xgate/trunk/
86 Add JTAG test tasks rehayes 4824d 10h /xgate/trunk/
85 Corrections to instruction set details example code, added test bench debugger. rehayes 5098d 19h /xgate/trunk/
84 Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. rehayes 5098d 20h /xgate/trunk/
83 Add subroutine quailifier. rehayes 5098d 20h /xgate/trunk/
82 Added debug module to assist in software debugging. rehayes 5099d 14h /xgate/trunk/
81 Initial checkin of the SKIPJACK encrypt/decrypt application program rehayes 5099d 15h /xgate/trunk/
80 Added IRQ bypass registers and Test bench appendix rehayes 5161d 15h /xgate/trunk/
79 Added IRQ bypass registers and Test bench appendix rehayes 5161d 15h /xgate/trunk/
78 Added IRQ bypass registers and Test bench appendix rehayes 5161d 15h /xgate/trunk/
77 Documentation update rehayes 5161d 15h /xgate/trunk/
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5184d 16h /xgate/trunk/
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5184d 17h /xgate/trunk/
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5189d 18h /xgate/trunk/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5189d 18h /xgate/trunk/
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5189d 18h /xgate/trunk/
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5190d 20h /xgate/trunk/
70 Updated with interrupt bypass controll registers. rehayes 5190d 20h /xgate/trunk/
69 New test to verify irq interrupt priority encoder. rehayes 5190d 21h /xgate/trunk/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5190d 21h /xgate/trunk/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5190d 21h /xgate/trunk/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5210d 17h /xgate/trunk/
65 Parameterize delays based on number of RAM wait states. rehayes 5210d 17h /xgate/trunk/
64 Fixed more bugs related to wait states and debug mode. rehayes 5210d 17h /xgate/trunk/
63 Remove historical output ports that are no longer used. rehayes 5220d 16h /xgate/trunk/

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