OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 97

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
95 Covers all 127 interrupts with one service routine. rehayes 4596d 14h /xgate/trunk/bench/verilog/
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4596d 14h /xgate/trunk/bench/verilog/
93 Initial revision, memory image for skipjack test. rehayes 4596d 15h /xgate/trunk/bench/verilog/
89 Code cleanup. rehayes 4610d 14h /xgate/trunk/bench/verilog/
86 Add JTAG test tasks rehayes 4810d 13h /xgate/trunk/bench/verilog/
82 Added debug module to assist in software debugging. rehayes 5085d 17h /xgate/trunk/bench/verilog/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5175d 20h /xgate/trunk/bench/verilog/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5177d 00h /xgate/trunk/bench/verilog/
65 Parameterize delays based on number of RAM wait states. rehayes 5196d 19h /xgate/trunk/bench/verilog/
62 Cleanup implicit wire declarations. rehayes 5206d 19h /xgate/trunk/bench/verilog/
60 Add ability at insert wait states on RAM access rehayes 5213d 19h /xgate/trunk/bench/verilog/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5281d 22h /xgate/trunk/bench/verilog/
50 incremental update to match status bit changes rehayes 5297d 19h /xgate/trunk/bench/verilog/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5332d 19h /xgate/trunk/bench/verilog/
37 RAM model breakout for testbench rehayes 5360d 23h /xgate/trunk/bench/verilog/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5360d 23h /xgate/trunk/bench/verilog/
35 Add byte lane select input to all tasks rehayes 5360d 23h /xgate/trunk/bench/verilog/
27 Subversion test, no actual code changes rehayes 5385d 17h /xgate/trunk/bench/verilog/
21 Added timeout, total error count, and XGCHN test rehayes 5393d 19h /xgate/trunk/bench/verilog/
20 Added event signal for compare error tracking in top level test bench. rehayes 5393d 19h /xgate/trunk/bench/verilog/
19 Verilog memory image for testing rehayes 5393d 19h /xgate/trunk/bench/verilog/
11 Update with Single Step debuging test rehayes 5407d 19h /xgate/trunk/bench/verilog/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5420d 19h /xgate/trunk/bench/verilog/
2 Initial Checkin rehayes 5428d 17h /xgate/trunk/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.