OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5206d 10h /xgate/trunk/rtl/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5258d 13h /xgate/trunk/rtl/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5274d 13h /xgate/trunk/rtl/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5290d 10h /xgate/trunk/rtl/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5324d 08h /xgate/trunk/rtl/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5324d 08h /xgate/trunk/rtl/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5325d 10h /xgate/trunk/rtl/
40 Update for single program counter adder rehayes 5345d 13h /xgate/trunk/rtl/
34 minor changes related to wishbone master interface rehayes 5353d 15h /xgate/trunk/rtl/
31 Cleanup for MAX_CHANNEL bus rehayes 5365d 10h /xgate/trunk/rtl/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5365d 10h /xgate/trunk/rtl/
29 Added some constant assigments, still needs more work to complete rehayes 5365d 10h /xgate/trunk/rtl/
28 Added comment line rehayes 5365d 10h /xgate/trunk/rtl/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5380d 11h /xgate/trunk/rtl/
25 Fix connected net name rehayes 5380d 11h /xgate/trunk/rtl/
24 Delete unused inputs rehayes 5380d 13h /xgate/trunk/rtl/
17 Additions for XGCHID debug commands rehayes 5386d 10h /xgate/trunk/rtl/
15 Fix R1 load at boot up, add debug features rehayes 5399d 08h /xgate/trunk/rtl/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5400d 10h /xgate/trunk/rtl/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5413d 10h /xgate/trunk/rtl/
2 Initial Checkin rehayes 5421d 08h /xgate/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.