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[/] [xgate/] [trunk/] [rtl/] - Rev 66

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Rev Log message Author Age Path
64 Fixed more bugs related to wait states and debug mode. rehayes 5228d 00h /xgate/trunk/rtl/
63 Remove historical output ports that are no longer used. rehayes 5238d 00h /xgate/trunk/rtl/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5245d 00h /xgate/trunk/rtl/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5297d 02h /xgate/trunk/rtl/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5313d 03h /xgate/trunk/rtl/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5329d 00h /xgate/trunk/rtl/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5362d 21h /xgate/trunk/rtl/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5362d 22h /xgate/trunk/rtl/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 00h /xgate/trunk/rtl/
40 Update for single program counter adder rehayes 5384d 02h /xgate/trunk/rtl/
34 minor changes related to wishbone master interface rehayes 5392d 05h /xgate/trunk/rtl/
31 Cleanup for MAX_CHANNEL bus rehayes 5404d 00h /xgate/trunk/rtl/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5404d 00h /xgate/trunk/rtl/
29 Added some constant assigments, still needs more work to complete rehayes 5404d 00h /xgate/trunk/rtl/
28 Added comment line rehayes 5404d 00h /xgate/trunk/rtl/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5419d 01h /xgate/trunk/rtl/
25 Fix connected net name rehayes 5419d 01h /xgate/trunk/rtl/
24 Delete unused inputs rehayes 5419d 02h /xgate/trunk/rtl/
17 Additions for XGCHID debug commands rehayes 5425d 00h /xgate/trunk/rtl/
15 Fix R1 load at boot up, add debug features rehayes 5437d 22h /xgate/trunk/rtl/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5439d 00h /xgate/trunk/rtl/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5452d 00h /xgate/trunk/rtl/
2 Initial Checkin rehayes 5459d 22h /xgate/trunk/rtl/

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