OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] - Rev 89

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
89 Code cleanup. rehayes 4613d 02h /xgate/trunk/rtl/
88 Updated with complete code rehayes 4686d 11h /xgate/trunk/rtl/
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4813d 01h /xgate/trunk/rtl/
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5173d 08h /xgate/trunk/rtl/
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5178d 09h /xgate/trunk/rtl/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5179d 12h /xgate/trunk/rtl/
64 Fixed more bugs related to wait states and debug mode. rehayes 5199d 08h /xgate/trunk/rtl/
63 Remove historical output ports that are no longer used. rehayes 5209d 08h /xgate/trunk/rtl/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5216d 07h /xgate/trunk/rtl/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5268d 10h /xgate/trunk/rtl/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5284d 11h /xgate/trunk/rtl/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5300d 08h /xgate/trunk/rtl/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 05h /xgate/trunk/rtl/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 05h /xgate/trunk/rtl/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5335d 07h /xgate/trunk/rtl/
40 Update for single program counter adder rehayes 5355d 10h /xgate/trunk/rtl/
34 minor changes related to wishbone master interface rehayes 5363d 12h /xgate/trunk/rtl/
31 Cleanup for MAX_CHANNEL bus rehayes 5375d 07h /xgate/trunk/rtl/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5375d 07h /xgate/trunk/rtl/
29 Added some constant assigments, still needs more work to complete rehayes 5375d 07h /xgate/trunk/rtl/
28 Added comment line rehayes 5375d 07h /xgate/trunk/rtl/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5390d 09h /xgate/trunk/rtl/
25 Fix connected net name rehayes 5390d 09h /xgate/trunk/rtl/
24 Delete unused inputs rehayes 5390d 10h /xgate/trunk/rtl/
17 Additions for XGCHID debug commands rehayes 5396d 07h /xgate/trunk/rtl/
15 Fix R1 load at boot up, add debug features rehayes 5409d 05h /xgate/trunk/rtl/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5410d 08h /xgate/trunk/rtl/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5423d 08h /xgate/trunk/rtl/
2 Initial Checkin rehayes 5431d 05h /xgate/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.