OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 Fix lint problems, change lowest interrupt vector from 0 to 1. rehayes 4203d 18h /xgate/trunk/rtl/
92 Add sync reset to bypass register. rehayes 4594d 21h /xgate/trunk/rtl/
89 Code cleanup. rehayes 4608d 20h /xgate/trunk/rtl/
88 Updated with complete code rehayes 4682d 05h /xgate/trunk/rtl/
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4808d 19h /xgate/trunk/rtl/
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5169d 02h /xgate/trunk/rtl/
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5174d 03h /xgate/trunk/rtl/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5175d 06h /xgate/trunk/rtl/
64 Fixed more bugs related to wait states and debug mode. rehayes 5195d 02h /xgate/trunk/rtl/
63 Remove historical output ports that are no longer used. rehayes 5205d 01h /xgate/trunk/rtl/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5212d 01h /xgate/trunk/rtl/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5264d 04h /xgate/trunk/rtl/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5280d 05h /xgate/trunk/rtl/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5296d 02h /xgate/trunk/rtl/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 23h /xgate/trunk/rtl/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 23h /xgate/trunk/rtl/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5331d 01h /xgate/trunk/rtl/
40 Update for single program counter adder rehayes 5351d 04h /xgate/trunk/rtl/
34 minor changes related to wishbone master interface rehayes 5359d 06h /xgate/trunk/rtl/
31 Cleanup for MAX_CHANNEL bus rehayes 5371d 01h /xgate/trunk/rtl/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5371d 01h /xgate/trunk/rtl/
29 Added some constant assigments, still needs more work to complete rehayes 5371d 01h /xgate/trunk/rtl/
28 Added comment line rehayes 5371d 01h /xgate/trunk/rtl/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5386d 02h /xgate/trunk/rtl/
25 Fix connected net name rehayes 5386d 02h /xgate/trunk/rtl/
24 Delete unused inputs rehayes 5386d 04h /xgate/trunk/rtl/
17 Additions for XGCHID debug commands rehayes 5392d 01h /xgate/trunk/rtl/
15 Fix R1 load at boot up, add debug features rehayes 5404d 23h /xgate/trunk/rtl/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5406d 01h /xgate/trunk/rtl/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5419d 01h /xgate/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.