| Rev |
Log message |
Author |
Age |
Path |
| 92 |
Add sync reset to bypass register. |
rehayes |
4610d 08h |
/xgate/trunk/rtl/verilog/ |
| 89 |
Code cleanup. |
rehayes |
4624d 07h |
/xgate/trunk/rtl/verilog/ |
| 88 |
Updated with complete code |
rehayes |
4697d 16h |
/xgate/trunk/rtl/verilog/ |
| 87 |
First pass JTAG TAP, state machine working but needs work to complete reset of TAP. |
rehayes |
4824d 07h |
/xgate/trunk/rtl/verilog/ |
| 75 |
Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 |
rehayes |
5184d 13h |
/xgate/trunk/rtl/verilog/ |
| 72 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5189d 14h |
/xgate/trunk/rtl/verilog/ |
| 67 |
Added irq bypass function and controll registers. Made lowest interrupt index highest priority. |
rehayes |
5190d 17h |
/xgate/trunk/rtl/verilog/ |
| 64 |
Fixed more bugs related to wait states and debug mode. |
rehayes |
5210d 13h |
/xgate/trunk/rtl/verilog/ |
| 63 |
Remove historical output ports that are no longer used. |
rehayes |
5220d 13h |
/xgate/trunk/rtl/verilog/ |
| 59 |
Fix bug in entering DEBUG mode from WB bus command |
rehayes |
5227d 13h |
/xgate/trunk/rtl/verilog/ |
| 57 |
Traded 16 data registers for 5 address regester when wait states are enabled. |
rehayes |
5279d 15h |
/xgate/trunk/rtl/verilog/ |
| 53 |
Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. |
rehayes |
5295d 16h |
/xgate/trunk/rtl/verilog/ |
| 47 |
Fix status bit error in ADC and SBC instruction, fix error in thread startup. |
rehayes |
5311d 13h |
/xgate/trunk/rtl/verilog/ |
| 43 |
Update for single program counter added, WISHBONE Slave bus word addressability and byte selection |
rehayes |
5345d 10h |
/xgate/trunk/rtl/verilog/ |
| 42 |
Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection |
rehayes |
5345d 10h |
/xgate/trunk/rtl/verilog/ |
| 41 |
Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection |
rehayes |
5346d 12h |
/xgate/trunk/rtl/verilog/ |
| 40 |
Update for single program counter adder |
rehayes |
5366d 15h |
/xgate/trunk/rtl/verilog/ |
| 34 |
minor changes related to wishbone master interface |
rehayes |
5374d 17h |
/xgate/trunk/rtl/verilog/ |
| 31 |
Cleanup for MAX_CHANNEL bus |
rehayes |
5386d 12h |
/xgate/trunk/rtl/verilog/ |
| 30 |
Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus |
rehayes |
5386d 12h |
/xgate/trunk/rtl/verilog/ |
| 29 |
Added some constant assigments, still needs more work to complete |
rehayes |
5386d 12h |
/xgate/trunk/rtl/verilog/ |
| 28 |
Added comment line |
rehayes |
5386d 13h |
/xgate/trunk/rtl/verilog/ |
| 26 |
Add synopsys commands, add else defaults for semphore state machine. |
rehayes |
5401d 14h |
/xgate/trunk/rtl/verilog/ |
| 25 |
Fix connected net name |
rehayes |
5401d 14h |
/xgate/trunk/rtl/verilog/ |
| 24 |
Delete unused inputs |
rehayes |
5401d 15h |
/xgate/trunk/rtl/verilog/ |
| 17 |
Additions for XGCHID debug commands |
rehayes |
5407d 12h |
/xgate/trunk/rtl/verilog/ |
| 15 |
Fix R1 load at boot up, add debug features |
rehayes |
5420d 10h |
/xgate/trunk/rtl/verilog/ |
| 12 |
Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits |
rehayes |
5421d 13h |
/xgate/trunk/rtl/verilog/ |
| 5 |
Update for memory wait states, testbench and instruction decoder simplified for synthesis |
rehayes |
5434d 13h |
/xgate/trunk/rtl/verilog/ |
| 2 |
Initial Checkin |
rehayes |
5442d 11h |
/xgate/trunk/rtl/verilog/ |
