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[/] [xge_mac/] [trunk/] - Rev 24

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Rev Log message Author Age Path
24 Use FIFO's for statistics clock domain crossing antanguay 4237d 23h /xge_mac/trunk/
23 Adding basic packet stats antanguay 4238d 05h /xge_mac/trunk/
22 Added prototype system verilog testbench antanguay 4240d 02h /xge_mac/trunk/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4240d 02h /xge_mac/trunk/
20 Updates for Xilinx synthesis antanguay 4529d 20h /xge_mac/trunk/
19 Updates for 32/64 bit systems antanguay 4704d 21h /xge_mac/trunk/
18 Updates for linux 32-bit antanguay 4705d 18h /xge_mac/trunk/
17 Fixed deprecated SystemC warnings antanguay 4708d 02h /xge_mac/trunk/
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4708d 08h /xge_mac/trunk/
15 Updated for Verilator 3.813 antanguay 4727d 09h /xge_mac/trunk/
14 Change interface to big endian, added serdes examples to testbench antanguay 5316d 03h /xge_mac/trunk/
13 Change interface to big endian, added serdes examples to testbench antanguay 5316d 04h /xge_mac/trunk/
12 Change interface to big endian, added serdes examples to testbench antanguay 5316d 04h /xge_mac/trunk/
11 Fixed clock crossing antanguay 5422d 01h /xge_mac/trunk/
10 Added details to spec antanguay 5519d 20h /xge_mac/trunk/
7 New directory structure. root 5594d 13h /xge_mac/trunk/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5870d 21h /trunk/
5 Fixed compilation antanguay 5876d 21h /trunk/
4 Created antanguay 5877d 00h /trunk/
2 Initial revision antanguay 5877d 01h /trunk/
1 Standard project directories initialized by cvs2svn. 5877d 01h /trunk/

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