| Rev |
Log message |
Author |
Age |
Path |
| 30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3050d 21h |
/xulalx25soc/ |
| 29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3051d 13h |
/xulalx25soc/ |
| 28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3051d 17h |
/xulalx25soc/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3051d 17h |
/xulalx25soc/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3051d 17h |
/xulalx25soc/ |
| 25 |
Fixing compile time warnings. |
dgisselq |
3051d 17h |
/xulalx25soc/ |
| 24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3057d 15h |
/xulalx25soc/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3060d 03h |
/xulalx25soc/ |
| 22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3062d 20h |
/xulalx25soc/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3113d 02h |
/xulalx25soc/ |
| 20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3113d 02h |
/xulalx25soc/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3113d 02h |
/xulalx25soc/ |
| 18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3116d 17h |
/xulalx25soc/ |
| 17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3116d 17h |
/xulalx25soc/ |
| 16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3116d 17h |
/xulalx25soc/ |
| 15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3118d 13h |
/xulalx25soc/ |
| 14 |
Quick bug fix. |
dgisselq |
3118d 13h |
/xulalx25soc/ |
| 13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3118d 13h |
/xulalx25soc/ |
| 12 |
Modified to match the settings I'm now using within ISE. |
dgisselq |
3118d 15h |
/xulalx25soc/ |
| 11 |
Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.) |
dgisselq |
3118d 15h |
/xulalx25soc/ |
| 10 |
Changed the name of the memtest.s file. |
dgisselq |
3118d 15h |
/xulalx25soc/ |
| 9 |
Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz. |
dgisselq |
3118d 15h |
/xulalx25soc/ |
| 8 |
Added an interface description to the comments at the top of the file. |
dgisselq |
3121d 01h |
/xulalx25soc/ |
| 7 |
Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault. |
dgisselq |
3121d 02h |
/xulalx25soc/ |
| 6 |
Initial file load, likely to be buggy, but the initial load nonetheless. |
dgisselq |
3121d 11h |
/xulalx25soc/ |
| 5 |
Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.) |
dgisselq |
3121d 12h |
/xulalx25soc/ |
| 4 |
Here's an initial, albeit incomplete, build. |
dgisselq |
3121d 12h |
/xulalx25soc/ |
| 3 |
|
dgisselq |
3121d 12h |
/xulalx25soc/ |
| 2 |
A very first, albeit incomplete, build. |
dgisselq |
3121d 12h |
/xulalx25soc/ |
| 1 |
The project and the structure was created |
root |
3121d 13h |
/xulalx25soc/ |
