| Rev |
Log message |
Author |
Age |
Path |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3001d 11h |
/xulalx25soc/trunk/rtl/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3001d 11h |
/xulalx25soc/trunk/rtl/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3005d 07h |
/xulalx25soc/trunk/rtl/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3005d 07h |
/xulalx25soc/trunk/rtl/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3005d 07h |
/xulalx25soc/trunk/rtl/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3008d 13h |
/xulalx25soc/trunk/rtl/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3009d 11h |
/xulalx25soc/trunk/rtl/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3013d 07h |
/xulalx25soc/trunk/rtl/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3013d 09h |
/xulalx25soc/trunk/rtl/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3013d 09h |
/xulalx25soc/trunk/rtl/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3014d 10h |
/xulalx25soc/trunk/rtl/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3014d 10h |
/xulalx25soc/trunk/rtl/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3022d 20h |
/xulalx25soc/trunk/rtl/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3075d 19h |
/xulalx25soc/trunk/rtl/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3075d 19h |
/xulalx25soc/trunk/rtl/ |
| 18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3079d 10h |
/xulalx25soc/trunk/rtl/ |
| 14 |
Quick bug fix. |
dgisselq |
3081d 06h |
/xulalx25soc/trunk/rtl/ |
| 9 |
Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz. |
dgisselq |
3081d 08h |
/xulalx25soc/trunk/rtl/ |
| 8 |
Added an interface description to the comments at the top of the file. |
dgisselq |
3083d 18h |
/xulalx25soc/trunk/rtl/ |
| 7 |
Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault. |
dgisselq |
3083d 19h |
/xulalx25soc/trunk/rtl/ |
| 6 |
Initial file load, likely to be buggy, but the initial load nonetheless. |
dgisselq |
3084d 05h |
/xulalx25soc/trunk/rtl/ |
| 3 |
|
dgisselq |
3084d 05h |
/xulalx25soc/trunk/rtl/ |
| 2 |
A very first, albeit incomplete, build. |
dgisselq |
3084d 05h |
/xulalx25soc/trunk/rtl/ |
