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[/] [xulalx25soc/] [trunk/] [sw/] - Rev 112

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Rev Log message Author Age Path
111 Added some debug support programs to the repository. dgisselq 2903d 14h /xulalx25soc/trunk/sw/
110 Fixed a problem whereby block RAM would be declared as a bus error on the
stack, even if the data was valid.
dgisselq 2903d 19h /xulalx25soc/trunk/sw/
109 This continues the updates to the wishbone-uart conversion. It fixes several
bugs within wbuexec, and pipelines the compression scheme. Further, the
read codeword was adjusted so that a read of 8 can be requested with six-bits,
rather than requiring 12. Likewise, the dependence upon the read of 8 on
incrementing the address pointer has been removed. All told, the design
builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing
flash seems to be one of the most comprehensive tests ...)
dgisselq 2903d 23h /xulalx25soc/trunk/sw/
105 Mostly cosmetic changes. The Makefile now builds a couple more programs,
the documentation is better, etc.
dgisselq 2904d 09h /xulalx25soc/trunk/sw/
104 Updates to the flash driver drawn from the S6SoC project. dgisselq 2904d 09h /xulalx25soc/trunk/sw/
103 Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.)
dgisselq 2904d 09h /xulalx25soc/trunk/sw/
93 Oops -- missed adjusting the copyright. dgisselq 2927d 14h /xulalx25soc/trunk/sw/
92 Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger.
dgisselq 2927d 14h /xulalx25soc/trunk/sw/
91 Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned.
dgisselq 2927d 14h /xulalx25soc/trunk/sw/
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.
dgisselq 2933d 10h /xulalx25soc/trunk/sw/
77 Adds register names and values for the SD card interface. dgisselq 2933d 10h /xulalx25soc/trunk/sw/
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.
dgisselq 2933d 10h /xulalx25soc/trunk/sw/
53 Added a touch of error checking. dgisselq 2981d 11h /xulalx25soc/trunk/sw/
49 Added some documentation to make the read and write calls easier to understand. dgisselq 3009d 12h /xulalx25soc/trunk/sw/
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.
dgisselq 3011d 14h /xulalx25soc/trunk/sw/
42 Minor changes. dgisselq 3015d 10h /xulalx25soc/trunk/sw/
41 Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier.
dgisselq 3015d 10h /xulalx25soc/trunk/sw/
40 This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb.
dgisselq 3016d 21h /xulalx25soc/trunk/sw/
38 Updated to remove the build dependence upon ZipCPU. dgisselq 3018d 20h /xulalx25soc/trunk/sw/
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.
dgisselq 3023d 12h /xulalx25soc/trunk/sw/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.
dgisselq 3023d 13h /xulalx25soc/trunk/sw/
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3023d 17h /xulalx25soc/trunk/sw/
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)
dgisselq 3024d 09h /xulalx25soc/trunk/sw/
28 Oops--two files needed by zipdbg weren't originally placed in the directory. dgisselq 3024d 13h /xulalx25soc/trunk/sw/
25 Fixing compile time warnings. dgisselq 3024d 14h /xulalx25soc/trunk/sw/
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3030d 12h /xulalx25soc/trunk/sw/
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)
dgisselq 3089d 13h /xulalx25soc/trunk/sw/
13 This version is now working. (It probably would've worked before, but
everything is now working.)
dgisselq 3091d 09h /xulalx25soc/trunk/sw/
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)
dgisselq 3091d 12h /xulalx25soc/trunk/sw/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.
dgisselq 3093d 22h /xulalx25soc/trunk/sw/

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