URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 102

Rev	Log message	Author	Age	Path
102	raname signals.	simont	7776d 19h	/
101	initial inport	simont	7776d 22h	/
100	use \	simont	7776d 22h	/
99	change directory structure	simont	7776d 23h	/
98	move to rtl/verilog	simont	7776d 23h	/
97	initial inport	simont	7776d 23h	/
96	initial import	simont	7776d 23h	/
95	updating...	simont	7776d 23h	/
94	fix bug.	simont	7776d 23h	/
93	OC8051_XILINX_RAM added	simont	7776d 23h	/
92	initial inport	simont	7776d 23h	/
91	* empty log message *	simont	7776d 23h	/
90	change module name.	simont	7781d 17h	/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7842d 20h	/
88	fix bugs	simont	7847d 20h	/
87	add include oc8051_defines.v	simont	7847d 20h	/
86	initial input	simont	7847d 21h	/
85	prepare bugs	simont	7847d 21h	/
84	remove wb_bus_mon	simont	7855d 20h	/
83	replace some modules	simont	7855d 20h	/
82	replace some modules	simont	7855d 20h	/
81	initial import	simont	7855d 20h	/
80	removing unused modules	simont	7855d 20h	/
79	initial import	simont	7855d 20h	/
78	alu with registered outputs	simont	7915d 20h	/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7924d 17h	/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7924d 17h	/
75	initial import	simont	7924d 17h	/
74	add module oc8051_wb_iinterface	simont	7932d 18h	/
73	initial import	simont	7932d 18h	/