OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

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Rev Log message Author Age Path
174 ram modules added. simont 7751d 01h /
173 simualtion `ifdef added simont 7751d 01h /
172 BIST signals added. simont 7754d 00h /
171 fix bug in DA operation. simont 7761d 22h /
170 removing unused files. simont 7761d 22h /
169 remove unused files. simont 7761d 22h /
168 modify program list. simont 7761d 23h /
167 add readmem for ea. simont 7765d 04h /
166 Change test monitor from ports to external data memory. simont 7765d 21h /
165 remove dumpvars. simont 7766d 02h /
164 initial inport. simont 7766d 03h /
163 initial inport simont 7766d 03h /
162 initial inport. simont 7766d 03h /
161 fix file names. simont 7766d 03h /
160 initial inport. simont 7766d 03h /
159 initial inport. simont 7766d 03h /
158 fix bug. simont 7766d 03h /
157 change data output. simont 7766d 03h /
156 add FREQ paremeter. simont 7766d 04h /
155 add aditional tests. simont 7766d 04h /
154 File name fixed. simont 7766d 22h /
153 `ifdef added. simont 7767d 21h /
152 sub_result output added. simont 7767d 21h /
151 remove pc_r register. simont 7767d 21h /
150 fix some bugs. simont 7767d 22h /
149 pipelined acces to axternal instruction interface added. simont 7767d 22h /
148 include "8051_defines" added. simont 7767d 22h /
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7789d 22h /
146 fix bug in movc intruction. simont 7789d 22h /
145 fix bug in case of sequence of inc dptr instrucitons. simont 7795d 02h /

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