OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 174

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
174 ram modules added. simont 7689d 16h /
173 simualtion `ifdef added simont 7689d 16h /
172 BIST signals added. simont 7692d 15h /
171 fix bug in DA operation. simont 7700d 13h /
170 removing unused files. simont 7700d 13h /
169 remove unused files. simont 7700d 13h /
168 modify program list. simont 7700d 14h /
167 add readmem for ea. simont 7703d 19h /
166 Change test monitor from ports to external data memory. simont 7704d 12h /
165 remove dumpvars. simont 7704d 16h /
164 initial inport. simont 7704d 17h /
163 initial inport simont 7704d 17h /
162 initial inport. simont 7704d 18h /
161 fix file names. simont 7704d 18h /
160 initial inport. simont 7704d 18h /
159 initial inport. simont 7704d 18h /
158 fix bug. simont 7704d 18h /
157 change data output. simont 7704d 18h /
156 add FREQ paremeter. simont 7704d 18h /
155 add aditional tests. simont 7704d 18h /
154 File name fixed. simont 7705d 13h /
153 `ifdef added. simont 7706d 12h /
152 sub_result output added. simont 7706d 12h /
151 remove pc_r register. simont 7706d 12h /
150 fix some bugs. simont 7706d 12h /
149 pipelined acces to axternal instruction interface added. simont 7706d 12h /
148 include "8051_defines" added. simont 7706d 13h /
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7728d 13h /
146 fix bug in movc intruction. simont 7728d 13h /
145 fix bug in case of sequence of inc dptr instrucitons. simont 7733d 17h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.