URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 184

Rev	Log message	Author	Age	Path
184	initial inport.	simont	7641d 23h	/
183	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7655d 10h	/
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7655d 10h	/
181	Simulation reports added.	simont	7655d 10h	/
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7655d 11h	/
179	add /* synopsys xx_case */ to case statments.	simont	7655d 11h	/
178	x replaced with 0.	simont	7655d 13h	/
177	Fix bug in case of writing and reading from same address.	simont	7666d 17h	/
176	ram modules added.	simont	7666d 18h	/
175	initial inport.	simont	7666d 19h	/
174	ram modules added.	simont	7666d 19h	/
173	simualtion `ifdef added	simont	7666d 19h	/
172	BIST signals added.	simont	7669d 18h	/
171	fix bug in DA operation.	simont	7677d 15h	/
170	removing unused files.	simont	7677d 16h	/
169	remove unused files.	simont	7677d 16h	/
168	modify program list.	simont	7677d 16h	/
167	add readmem for ea.	simont	7680d 22h	/
166	Change test monitor from ports to external data memory.	simont	7681d 15h	/
165	remove dumpvars.	simont	7681d 19h	/
164	initial inport.	simont	7681d 20h	/
163	initial inport	simont	7681d 20h	/
162	initial inport.	simont	7681d 20h	/
161	fix file names.	simont	7681d 21h	/
160	initial inport.	simont	7681d 21h	/
159	initial inport.	simont	7681d 21h	/
158	fix bug.	simont	7681d 21h	/
157	change data output.	simont	7681d 21h	/
156	add FREQ paremeter.	simont	7681d 21h	/
155	add aditional tests.	simont	7681d 21h	/