URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 35

Rev	Log message	Author	Age	Path
35	design docunemt	simont	7978d 01h	/
34	specification docunemt	simont	7978d 01h	/
33	fix some bugs	simont	7978d 07h	/
32	overflow repaired	simont	7978d 07h	/
31	fix some bugs	simont	7984d 23h	/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7988d 06h	/
29	fix some bugs	simont	7988d 07h	/
28	remove syn signal	simont	7988d 07h	/
27	fix some bugs	simont	7988d 07h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7988d 09h	/
25	divider and multiplier pass test	markom	7989d 03h	/
24	intensively tests all instructions	markom	7989d 08h	/
23	mul & div use 4 clocks	simont	7989d 23h	/
22	fix some bugs	simont	7989d 23h	/
21	mul bug fixed	markom	7990d 04h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	7990d 06h	/
19	combinatorial loop removed	simont	7990d 23h	/
18	rst signal added	simont	7994d 04h	/
17	fix some bugs	simont	7994d 04h	/
16	inputs ram and op2 removed	simont	7994d 04h	/
15	commbinatorial loop removed	simont	7994d 04h	/
14	added signal ea_int	simont	7994d 05h	/
13	some bug fix	simont	7995d 02h	/
12	des1_r in alu port list	simont	7995d 02h	/
11	des2_r removed	simont	7995d 02h	/
10	% replaced with ^ in uart; some minor improvements	markom	7995d 08h	/
9	removed unused compare states	markom	7997d 01h	/
8	some IDS optimizations	markom	7997d 01h	/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	7997d 03h	/
6	psw combinatorial loop removed	markom	7997d 05h	/