OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 53

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4687d 13h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4687d 13h /
51 Revert vmlinux back to 48. csantifort 4728d 13h /
50 Revert to previous version csantifort 4728d 13h /
49 Added a note n how to change timeouts csantifort 4728d 13h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 4732d 20h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4752d 17h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4760d 15h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4760d 15h /
44 Updated vmlinux image based on last change csantifort 4760d 15h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4760d 15h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4778d 12h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4779d 20h /
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 4784d 13h /
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 4785d 14h /
38 support 128-bit wishbone now used for a25 core csantifort 4786d 13h /
37 128-bit wide boot memory module csantifort 4787d 12h /
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4787d 13h /
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts		 csantifort 4788d 20h /
34 Tweaked strcpy function to speed it up slightly csantifort 4789d 17h /
33 Fixed bug in div assembly function. Handles negative numbers correctly.
Fixed bug in printf function, negative numbers now print correctly.		 csantifort 4790d 13h /
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 4791d 13h /
31 Added dhrystone benchmark test csantifort 4791d 14h /
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4804d 20h /
29 Use lgo command for saving waveforms in modelsim csantifort 4806d 13h /
28 Moved function prototypes to .h file csantifort 4806d 14h /
27 Got working with cadence nc simulator csantifort 4839d 21h /
26 Added wish list csantifort 4844d 21h /
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh		 csantifort 4846d 18h /
24 Added instructions how to build Linux kernel from source files csantifort 4848d 18h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.