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Rev Log message Author Age Path
78 pass link wsong0210 4719d 06h /
77 pass syn elaboration wsong0210 4720d 05h /
76 fix syntex wsong0210 4724d 06h /
75 code finished, start the debugging wsong0210 4724d 06h /
74 in/out buffer finished wsong0210 4725d 06h /
73 input buffer wsong0210 4732d 05h /
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4733d 05h /
71 the buffered 2-stage Clos switch wsong0210 4734d 05h /
70 clos-opt ongoing wsong0210 4734d 05h /
69 central module of the Clos wsong0210 4737d 05h /
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4738d 06h /
67 structure not good, prepare to use new files wsong0210 4738d 07h /
66 clos opt ongoing wsong0210 4753d 00h /
65 pipeline controller wsong0210 4753d 00h /
64 clos opt ongoing wsong0210 4753d 00h /
63 clos opt ongoing wsong0210 4753d 05h /
62 clos opt ongoing wsong0210 4754d 06h /
61 settle down the pipeline controller wsong0210 4759d 05h /
60 try to make the address comparison relaxed QDI wsong0210 4762d 06h /
59 address deduction wsong0210 4764d 05h /
58 opt ongoing 10/06/2011 wsong0210 4765d 06h /
57 insert buffers inside clos wsong0210 4765d 08h /
56 the first released version of Wormhole/SDM/VC wsong0210 4766d 06h /
55 merge reference list wsong0210 4766d 06h /
54 reference list wsong0210 4766d 06h /
53 merge from branch for doc wsong0210 4766d 06h /
52 schematic for SDM router wsong0210 4766d 06h /
51 add a C-element in all demux to ensure the sel pin is considered in the ack signal wsong0210 4766d 07h /
50 strange, merge does not work properly wsong0210 4767d 06h /
49 merge in process wsong0210 4767d 06h /

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