URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

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Rev	Log message	Author	Age	Path
82	correct some typoes, thanks to Hu, Tao	wsong0210	4012d 02h	/
81	adding a solution in README to a cell lib problem.	wsong0210	4380d 01h	/
80	make the README file more understandable	wsong0210	4459d 22h	/
79	update comments in sim compile.sh to clarify that synthesis must be done before post-synthesis simulation	wsong0210	4520d 08h	/
78	pass link	wsong0210	4686d 19h	/
77	pass syn elaboration	wsong0210	4687d 19h	/
76	fix syntex	wsong0210	4691d 19h	/
75	code finished, start the debugging	wsong0210	4691d 19h	/
74	in/out buffer finished	wsong0210	4692d 19h	/
73	input buffer	wsong0210	4699d 18h	/
72	clos-opt ongoing, Clos switch finished, nxt input buffer	wsong0210	4700d 19h	/
71	the buffered 2-stage Clos switch	wsong0210	4701d 19h	/
70	clos-opt ongoing	wsong0210	4701d 19h	/
69	central module of the Clos	wsong0210	4704d 19h	/
68	rewite the clos switch in the SDM-Clos-buf router	wsong0210	4705d 19h	/
67	structure not good, prepare to use new files	wsong0210	4705d 20h	/
66	clos opt ongoing	wsong0210	4720d 13h	/
65	pipeline controller	wsong0210	4720d 14h	/
64	clos opt ongoing	wsong0210	4720d 14h	/
63	clos opt ongoing	wsong0210	4720d 18h	/
62	clos opt ongoing	wsong0210	4721d 19h	/
61	settle down the pipeline controller	wsong0210	4726d 18h	/
60	try to make the address comparison relaxed QDI	wsong0210	4729d 19h	/
59	address deduction	wsong0210	4731d 18h	/
58	opt ongoing 10/06/2011	wsong0210	4732d 19h	/
57	insert buffers inside clos	wsong0210	4732d 21h	/
56	the first released version of Wormhole/SDM/VC	wsong0210	4733d 19h	/
55	merge reference list	wsong0210	4733d 19h	/
54	reference list	wsong0210	4733d 19h	/
53	merge from branch for doc	wsong0210	4733d 19h	/

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Subversion Repositories async_sdm_noc

[/] - Rev 82

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