OpenCores
URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] - Rev 25

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 Added AXI Passthrough Monitor IP for Vivado IP Integrator.
Can be synthesized by Vivado, but cannot be detected in the Vivado GUI.
Tk GUI can run with ISE/PLanahead 14.3 or 14.7.		 ash_riple 3546d 20h /
24 Added support for Qsys based avalon transaction monitoring. ash_riple 3566d 20h /
23 Updated Altera Tcl script to 32bit address bus. ash_riple 3773d 18h /
22 ash_riple 3773d 23h /
21 ash_riple 3774d 01h /
20 Added support for 32bit Address bus. ash_riple 3774d 01h /
19 Minor changes. ash_riple 4187d 19h /
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.		 ash_riple 4187d 20h /
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4433d 23h /
16 Released version 2.2. ash_riple 4455d 23h /
15 Released version 2.2. ash_riple 4455d 23h /
14 Changed dec to hex value of triggerPnum. ash_riple 4456d 14h /
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4456d 19h /
12 Added timing information to the capture content. ash_riple 4457d 03h /
11 Added pre-trigger capture. ash_riple 4457d 19h /
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4463d 00h /
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.		 ash_riple 4463d 19h /
8 Added fault handling of wrong input length in the GUI. ash_riple 4467d 19h /
7 Added references related to "Bus Monitor". ash_riple 4467d 23h /
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4468d 19h /
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.		 ash_riple 4471d 20h /
4 Created tag for original source code. Version 1.0. ash_riple 4471d 22h /
3 Added original article. ash_riple 4471d 22h /
2 Checked in working code base. ash_riple 4475d 19h /
1 The project and the structure was created root 4476d 09h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.