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Rev Log message Author Age Path
23 Fixed problem with wishbone wait-states jsauermann 6949d 15h /
22 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'. 6949d 20h /
21 Changes for Xilinx Proj. Nav. 7.1.02i jsauermann 6949d 20h /
20 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'. 7145d 17h /
19 FPGA Pin desription added. jsauermann 7145d 17h /
18 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7446d 16h /
17 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7446d 16h /
16 Enable interrupts at start of each task.
This fix is required after a change in opcode_decoder.vhd.		 jsauermann 7446d 16h /
15 sample ucf file jsauermann 7485d 19h /
14 no message jsauermann 7493d 20h /
13 bug in print_unsigned() fixed.
Now done as in rtos.c		 jsauermann 7536d 14h /
12 Todo removed jsauermann 7565d 12h /
11 First Version jsauermann 7565d 12h /
10 Set top of stack of idle task to end of internal memory rather
than end of external memory (causing incorrect display of
100 % CPU load).		 jsauermann 7565d 13h /
9 Made cpu_engine WISHBONE compliant.
(Somebody please validate it).		 jsauermann 7565d 14h /
8 Initialization of compound auto variables added (was TODO) jsauermann 7572d 16h /
7 Handle auto variable declarations in compound statements properly jsauermann 7573d 16h /
6 New Target polled for testing compiler without the need to simulate interrupts jsauermann 7573d 16h /
5 Initial version jsauermann 7574d 13h /
4 Documentation finalized jsauermann 7574d 17h /
3 This commit was manufactured by cvs2svn to create tag 'V10'. 7577d 12h /
2 no message jsauermann 7577d 12h /
1 Standard project directories initialized by cvs2svn. 7577d 12h /

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