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Rev Log message Author Age Path
26 New directory structure. root 5579d 15h /
25 XOR bug fixed jsauermann 6637d 22h /
24 no message jsauermann 6798d 20h /
23 Fixed problem with wishbone wait-states jsauermann 6938d 20h /
22 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'. 6939d 01h /
21 Changes for Xilinx Proj. Nav. 7.1.02i jsauermann 6939d 01h /
20 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'. 7134d 22h /
19 FPGA Pin desription added. jsauermann 7134d 22h /
18 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7435d 21h /
17 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7435d 21h /
16 Enable interrupts at start of each task.
This fix is required after a change in opcode_decoder.vhd.		 jsauermann 7435d 21h /
15 sample ucf file jsauermann 7475d 00h /
14 no message jsauermann 7483d 01h /
13 bug in print_unsigned() fixed.
Now done as in rtos.c		 jsauermann 7525d 18h /
12 Todo removed jsauermann 7554d 16h /
11 First Version jsauermann 7554d 16h /
10 Set top of stack of idle task to end of internal memory rather
than end of external memory (causing incorrect display of
100 % CPU load).		 jsauermann 7554d 18h /
9 Made cpu_engine WISHBONE compliant.
(Somebody please validate it).		 jsauermann 7554d 18h /
8 Initialization of compound auto variables added (was TODO) jsauermann 7561d 21h /
7 Handle auto variable declarations in compound statements properly jsauermann 7562d 20h /
6 New Target polled for testing compiler without the need to simulate interrupts jsauermann 7562d 21h /
5 Initial version jsauermann 7563d 18h /
4 Documentation finalized jsauermann 7563d 22h /
3 This commit was manufactured by cvs2svn to create tag 'V10'. 7566d 17h /
2 no message jsauermann 7566d 17h /
1 Standard project directories initialized by cvs2svn. 7566d 17h /

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