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Rev	Log message	Author	Age	Path
108	Fixed according to the linter.	mohor	7659d 23h	/
107	Fixed according to the linter.	mohor	7660d 00h	/
106	Unused signal removed.	mohor	7665d 21h	/
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7666d 11h	/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7666d 11h	/
103	This commit was manufactured by cvs2svn to create tag 'complete_1'.		7669d 02h	/
102	Little fixes (to fix warnings).	mohor	7669d 02h	/
101	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7673d 03h	/
100	Synchronization changed.	mohor	7673d 03h	/
99	PCI_BIST replaced with CAN_BIST.	mohor	7673d 03h	/
98	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7678d 15h	/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7678d 15h	/
96	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7678d 16h	/
95	Virtual silicon ram instances added.	simons	7678d 16h	/
94	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7684d 03h	/
93	synthesis full_case parallel_case fixed.	mohor	7684d 03h	/
92	clkout is clk/2 after the reset.	mohor	7684d 11h	/
91	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7685d 01h	/
90	paralel_case and full_case compiler directives added to case statements.	mohor	7685d 01h	/
89	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7685d 22h	/
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7685d 22h	/
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7685d 23h	/
86	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7687d 14h	/
85	Typo fixed.	mohor	7687d 14h	/
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7688d 21h	/
83	cs_can_i is used only when WISHBONE interface is not used.	mohor	7688d 22h	/
82	Removed few signals.	mohor	7688d 22h	/
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7688d 22h	/
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7688d 22h	/
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7689d 22h	/

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