OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 150

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7160d 10h /
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7160d 10h /
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7162d 17h /
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.
igorm 7162d 17h /
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7162d 22h /
145 Arbitration bug fixed. igorm 7162d 22h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7309d 14h /
143 Bit acceptance_filter_mode was inverted. igorm 7309d 14h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7328d 13h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7328d 13h /
140 I forgot to thange one signal name. igorm 7383d 11h /
139 Signal bus_off_on added. igorm 7383d 11h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7422d 14h /
137 Header changed. mohor 7422d 14h /
136 Error counters changed. mohor 7422d 14h /
135 Header changed. mohor 7422d 14h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7530d 12h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7536d 23h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7536d 23h /
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7536d 23h /
130 mbist signals updated according to newest convention markom 7536d 23h /
129 Error counters changed. mohor 7553d 07h /
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7553d 08h /
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7553d 08h /
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7554d 04h /
125 Synchronization changed, error counters fixed. mohor 7558d 10h /
124 ALTERA_RAM supported. mohor 7578d 16h /
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7585d 21h /
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7585d 21h /
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7585d 21h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.