OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 *** empty log message *** mohor 7772d 21h /
63 ALE changes on negedge of clk. mohor 7778d 19h /
62 can_cs signal used for generation of the cs. mohor 7778d 19h /
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.
mohor 7781d 08h /
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.
mohor 7781d 09h /
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7781d 10h /
58 timescale.v is used for simulation only. mohor 7781d 22h /
57 Mux used for clkout to avoid "gated clocks warning". mohor 7781d 22h /
56 Doubled declarations removed. mohor 7782d 21h /
55 wire declaration added. mohor 7782d 21h /
54 This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'. 7787d 23h /
53 CAN pins located. mohor 7787d 23h /
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7787d 23h /
51 Xilinx RAM added. mohor 7787d 23h /
50 Top level signal names changed. mohor 7787d 23h /
49 Actel APA ram changed. Now synchronous read is used. mohor 7791d 15h /
48 Actel APA ram supported. mohor 7791d 15h /
47 Data is latched on read. mohor 7791d 15h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7801d 14h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7801d 14h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7801d 15h /
43 Directory keeper. mohor 7801d 21h /
42 Initial version of the project. mohor 7801d 21h /
41 Incomplete sensitivity list fixed. mohor 7801d 23h /
40 Typo fixed. mohor 7801d 23h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7801d 23h /
38 Temporary backup version (still fully operable). mohor 7803d 14h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7803d 14h /
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 7803d 14h /
35 Several registers added. Not finished, yet. mohor 7806d 18h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.