URL https://opencores.org/ocsvn/common/common/trunk

Subversion Repositories common

[/] - Rev 38

Rev	Log message	Author	Age	Path
38	Undeleted	mohor	8023d 21h	/
37	no message	bbeaver	8260d 03h	/
36	minor changes: unified with all common rams	samg	8280d 12h	/
35	corrected output: output not valid if ce low	samg	8280d 17h	/
34	added valid checks to behvioral model	samg	8280d 18h	/
33	added checks and task in behavioral section	samg	8281d 19h	/
32	no message	bbeaver	8283d 00h	/
31	no message	bbeaver	8287d 01h	/
30	no message	bbeaver	8287d 23h	/
29	got timing checks mostly correct No functional stuff yet	bbeaver	8288d 00h	/
28	no message	bbeaver	8289d 00h	/
27	no message	bbeaver	8290d 00h	/
26	no message	bbeaver	8290d 23h	/
25	no message	bbeaver	8292d 01h	/
24	no message	bbeaver	8294d 02h	/
23	no message	bbeaver	8295d 01h	/
22	no message	bbeaver	8295d 05h	/
21	Added bookmarks.	lampret	8295d 18h	/
20	Some minor fixes. Document is now official version.	lampret	8295d 19h	/
19	no message	bbeaver	8297d 02h	/
18	no message	bbeaver	8298d 00h	/
17	Fixed link to specification_template.dot	lampret	8298d 09h	/
16	Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word.	lampret	8298d 10h	/
15	no message	bbeaver	8318d 06h	/
14	adding beginning LPM files	bbeaver	8330d 03h	/
13	This commit was manufactured by cvs2svn to create tag 'initial'.		8336d 03h	/
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8336d 03h	/
11	no message	bbeaver	8343d 01h	/
10	no message	bbeaver	8343d 01h	/
9	no message	bbeaver	8346d 23h	/