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[/] - Rev 42

Rev	Log message	Author	Age	Path
42	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7943d 09h	/
41	Changed synthesizeable FPGA memory implementation. Fixed some issues with Xilinx BlockRAM	rherveille	7943d 09h	/
40	Updated PDF.	lampret	7987d 12h	/
39	Added Richard's feedback.	lampret	7989d 13h	/
38	Undeleted	mohor	8010d 02h	/
37	no message	bbeaver	8246d 08h	/
36	minor changes: unified with all common rams	samg	8266d 17h	/
35	corrected output: output not valid if ce low	samg	8266d 22h	/
34	added valid checks to behvioral model	samg	8266d 22h	/
33	added checks and task in behavioral section	samg	8267d 23h	/
32	no message	bbeaver	8269d 05h	/
31	no message	bbeaver	8273d 05h	/
30	no message	bbeaver	8274d 04h	/
29	got timing checks mostly correct No functional stuff yet	bbeaver	8274d 05h	/
28	no message	bbeaver	8275d 05h	/
27	no message	bbeaver	8276d 05h	/
26	no message	bbeaver	8277d 04h	/
25	no message	bbeaver	8278d 05h	/
24	no message	bbeaver	8280d 07h	/
23	no message	bbeaver	8281d 06h	/
22	no message	bbeaver	8281d 10h	/
21	Added bookmarks.	lampret	8281d 23h	/
20	Some minor fixes. Document is now official version.	lampret	8281d 23h	/
19	no message	bbeaver	8283d 07h	/
18	no message	bbeaver	8284d 05h	/
17	Fixed link to specification_template.dot	lampret	8284d 13h	/
16	Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word.	lampret	8284d 14h	/
15	no message	bbeaver	8304d 11h	/
14	adding beginning LPM files	bbeaver	8316d 07h	/
13	This commit was manufactured by cvs2svn to create tag 'initial'.		8322d 07h	/