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Subversion Repositories csa

[/] - Rev 34

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Rev	Log message	Author	Age	Path
34	add binary test date (only sw_sim now )	simon111	5549d 15h	/
33	improve ledseg controler module	simon111	5550d 03h	/
32	fix a compile error	simon111	5550d 03h	/
31	remove pc execute file	simon111	5550d 04h	/
30	begin vailating on fpga	simon111	5550d 04h	/
29	fix some bugs	simon111	5551d 03h	/
28	create a quartus10 project for test the core	simon111	5551d 03h	/
27	improve makefiles	simon111	5551d 15h	/
26	Added old uploaded documents to new repository.	root	5587d 04h	/
25	Added old uploaded documents to new repository.	root	5587d 20h	/
24	New directory structure.	root	5587d 20h	/
23	testing key_schedule module	simon111	5671d 04h	/
22	decrypt module testbench update	simon111	5711d 03h	/
21	decrypt module passed basicly, it's not good code type	simon111	5711d 03h	/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5725d 02h	/
19	add a modelsim project to samulate the stream_cypher module	simon111	5725d 02h	/
18	try to add decrypt module (not finished yet)	simon111	5735d 04h	/
17	finish block_decypher module	simon111	5786d 10h	/
16	add the block_perm and block_sbox	simon111	5790d 02h	/
15	finished key_schedule module	simon111	5794d 03h	/
14	* empty log message *	simon111	5795d 04h	/
13	add key_schedule module(note: this module is not right yet)	simon111	5795d 04h	/
12	* empty log message *	simon111	5795d 04h	/
11	add clean rule for some makefile	simon111	5828d 05h	/
10	add the sw simulate stuff for key_perm	simon111	5828d 05h	/
9	add the pli module and bench for key_perm module	simon111	5828d 05h	/
8	initial version	simon111	5828d 05h	/
7	fix the key_perm module	simon111	5828d 05h	/
6	This commit was manufactured by cvs2svn to create tag 'arelease'.		6137d 02h	/
5	This commit was generated by cvs2svn to compensate for changes in r4, which included commits to RCS files with non-trunk default branches.	Simon111	6137d 02h	/

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Subversion Repositories csa

[/] - Rev 34

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