URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] - Rev 52

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Rev	Log message	Author	Age	Path
52	add the macro DEBUG_OUTPUT for the general debug information output	simon111	5158d 05h	/
51	remove the using to iverilog and veriwell	simon111	5508d 07h	/
50	add some documents	simon111	5508d 22h	/
49	group_decrypt module simulate success	simon111	5514d 19h	/
48	improve key_schedule module	simon111	5519d 19h	/
47	add bin prepare function	simon111	5519d 22h	/
46	delete key_comupter module and testbench	simon111	5520d 05h	/
45	improve makefile	simon111	5521d 23h	/
44	improve some module , strip warnings	simon111	5523d 19h	/
43	improve group_decrypt module	simon111	5523d 21h	/
42	add group_decrypt module	simon111	5524d 03h	/
41	add three moudule ts_serial_out ts_sync key_cnt	simon111	5524d 16h	/
40	add timescale.v file and fix a bug in key_schedule module	simon111	5524d 20h	/
39	add usb controler module	simon111	5524d 23h	/
38	improve the ledseg control module the register h must be 2bits width	simon111	5525d 17h	/
37	improve write_data systemcall,	simon111	5525d 23h	/
36	improve read_date vpi sytemcall, add offset and size argument	simon111	5526d 00h	/
35	csa cli support binary test data	simon111	5526d 04h	/
34	add binary test date (only sw_sim now )	simon111	5526d 07h	/
33	improve ledseg controler module	simon111	5526d 18h	/
32	fix a compile error	simon111	5526d 18h	/
31	remove pc execute file	simon111	5526d 19h	/
30	begin vailating on fpga	simon111	5526d 19h	/
29	fix some bugs	simon111	5527d 19h	/
28	create a quartus10 project for test the core	simon111	5527d 19h	/
27	improve makefiles	simon111	5528d 06h	/
26	Added old uploaded documents to new repository.	root	5563d 19h	/
25	Added old uploaded documents to new repository.	root	5564d 12h	/
24	New directory structure.	root	5564d 12h	/
23	testing key_schedule module	simon111	5647d 19h	/

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[/] - Rev 52

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