URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 26

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Rev	Log message	Author	Age	Path
26	Warnings from synthesys tools fixed.	mohor	8252d 17h	/
25	trst signal is synchronized to wb_clk_i.	mohor	8253d 14h	/
24	CRC changed so more thorough testing is done.	mohor	8254d 15h	/
23	Trace disabled by default.	mohor	8260d 17h	/
22	Register length fixed.	mohor	8260d 17h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8261d 13h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8262d 16h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8274d 17h	/
18	Reset signals are not combined any more.	mohor	8277d 02h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8300d 15h	/
16	bs_chain_o port added.	mohor	8302d 15h	/
15	bs_chain_o added.	mohor	8302d 16h	/
14	Document updated.	mohor	8303d 14h	/
13	Signal names changed to lowercase.	mohor	8303d 17h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8304d 17h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8325d 13h	/
10	First official release 1.0.	mohor	8329d 17h	/
9	Working version. Few bugs fixed, comments added.	mohor	8329d 17h	/
8	Asynchronous set/reset not used in trace any more.	mohor	8330d 15h	/
7	First official release 1.0.	mohor	8330d 15h	/
6	Minor changes for simulation.	mohor	8330d 15h	/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8331d 13h	/
4	Initial official release.	mohor	8336d 13h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		8336d 13h	/
2	Initial official release.	mohor	8336d 13h	/
1	Standard project directories initialized by cvs2svn.		8336d 13h	/

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Subversion Repositories dbg_interface

[/] - Rev 26

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