OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 67

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7581d 21h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7582d 20h /
65 WB_CNTL register added, some syncronization fixes. simons 7582d 20h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7602d 21h /
63 Three more chains added for cpu debug access. simons 7602d 21h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7630d 21h /
61 Lapsus fixed. simons 7630d 21h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7630d 21h /
59 Reset value for riscsel register set to 1. simons 7630d 21h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7630d 22h /
57 Multiple cpu support added. simons 7630d 22h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7897d 19h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7897d 19h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7897d 20h /
53 Trst active high. Inverted on higher layer. mohor 7897d 20h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7897d 20h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7925d 08h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7925d 09h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8080d 20h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8080d 20h /
47 mon_cntl_o signals that controls monitor mux added. mohor 8080d 20h /
46 Asynchronous reset used instead of synchronous. mohor 8089d 02h /
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8095d 22h /
44 Signal names changed to lower case. mohor 8095d 22h /
43 Intentional error removed. mohor 8100d 21h /
42 A block for checking possible simulation/synthesis missmatch added. mohor 8100d 23h /
41 Function changed to logic because of some synthesis warnings. mohor 8108d 20h /
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8122d 20h /
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8123d 21h /
38 Few outputs for boundary scan chain added. mohor 8136d 20h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.