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Rev Log message Author Age Path
80 New version of the debug interface. Not finished, yet. mohor 7493d 01h /
79 This commit was manufactured by cvs2svn to create tag 'rev_11'. 7553d 22h /
78 This commit was manufactured by cvs2svn to create tag 'old_debug'. 7553d 22h /
77 MBIST chain connection fixed. mohor 7553d 22h /
76 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7553d 23h /
75 Simulation files. mohor 7553d 23h /
74 Removed. mohor 7553d 23h /
73 CRC logic changed. mohor 7553d 23h /
72 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7556d 06h /
71 Mbist support added. simons 7556d 06h /
70 A pdf copy of existing doc document. simons 7563d 08h /
69 WBCNTL added, multiple CPU support described. simons 7583d 21h /
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7589d 02h /
67 Lower two address lines must be always zero. simons 7589d 02h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7590d 01h /
65 WB_CNTL register added, some syncronization fixes. simons 7590d 01h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7610d 02h /
63 Three more chains added for cpu debug access. simons 7610d 02h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7638d 02h /
61 Lapsus fixed. simons 7638d 02h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7638d 02h /
59 Reset value for riscsel register set to 1. simons 7638d 02h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7638d 03h /
57 Multiple cpu support added. simons 7638d 03h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7905d 00h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7905d 00h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7905d 01h /
53 Trst active high. Inverted on higher layer. mohor 7905d 01h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7905d 01h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7932d 13h /

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